(a) Field of the Invention
The present invention relates to a BGA (ball gird array) semiconductor device having a dummy bump and a method for manufacturing the same and, more particularly, to the structure of a BGA semiconductor device in which a semiconductor package and a wiring board are coupled together using a BGA technique.
(b) Description of the Related Art
A BGA technique is known in the art in which a semiconductor package including therein an IC chip is mounted on a wiring board (mounting board) by using an array of ball pins. The BGA technique has advantages of an increased number of package pins and a smaller size of the semiconductor package, which is substantially equivalent to the chip size. The semiconductor device including a semiconductor package and a mounting board coupled together via the BGA is referred to as a BGA semiconductor device in this text. Due to the advantages as described above, the BGA semiconductor devices are increasingly used in portable electronic equipment, such as a mobile telephone, which are ever required to reduce the dimensions thereof.
A variety of pin arrangements are generally used in the current BGA semiconductor devices depending on the bit length of the signals used therein. For the purpose of making standards for the pin arrangements, there are some BGA semiconductor devices in which the center of the pin array is deviated from the center of the semiconductor package depending on the bit length. FIG. 11A shows an example of this type of pin arrangement of the conventional BGA semiconductor device, which is generally designated by numeral 100. In the drawing, the center of the array of ball pins (signal ball pins) 13 is deviated from the central line 101 of the semiconductor package.
FIG. 11B shows a sectional view of the BGA semiconductor device of FIG. 11A, taken along line b-b in FIG. 11A. The BGA semiconductor device 100 includes a mounting board 11 and a semiconductor package 12 mounted thereon. The semiconductor package 12 includes therein a package substrate 15, an IC chip 16 mounted thereon, and a resin body 17 encapsulating the IC chip 16 on the package substrate 15.
An array of lands (or electrodes) 18 are formed on the mounting board 11 corresponding to the array of ball pins 13, the lands 18 being exposed from respective openings 19 of a solder resist film 20 formed on the mounting board 11. An array of lands (electrodes) 23A are also formed on the package substrate 15 for mounting thereon the ball pins 13, the lands 23A being exposed from openings 21 of a solder resist film 22 formed on the package substrate 15.
The ball pins include the signal ball pins or signal bumps 13 as described above, and also include dummy ball pins (dummy bumps) 14, which are disposed for reinforcing the bending strength of the BGA semiconductor device 100 including the mounting board 11 and the semiconductor package 12. The dummy bumps 14 are disposed in the vicinity of the periphery of the BGA semiconductor device 100 where the signal bumps 13 are not disposed. In this example of the BGA semiconductor device 100, a fan-in structure is employed wherein all the bumps 13 and 14 are disposed just below the IC chip 16.
It is noted that the mounting board 11, which is configured by an insulator such as epoxy resin and wiring patterns, has a thermal expansion coefficient different from that of the semiconductor package 12, with the result that the bumps 13 and 14 are subjected to stresses caused by heat cycles during fabrication or use of the semiconductor device 100. The stress applied to the bumps 13 and 14 is generally in proportion to a product of the distance between bumps and the thermal expansion coefficient, and accordingly, a maximum stress is applied to the bumps disposed in the vicinities of the corners of the BGA semiconductor device 100. If a signal bump 13A in the vicinity of a corner is damaged and broken down by the maximum stress, the BGA semiconductor device 100 cannot perform a normal operation.
JP Patent Appln. Publication 2001-68594 describes a technique for preventing the break-down of the signal bump in the vicinity of the corner of the BGA semiconductor device. The described technique uses a reinforcement land (pad) and a reinforcement dummy bump for increasing a shearing strength of signal bumps in the vicinities of corners of the semiconductor device. FIG. 13 shows the configuration of the BGA semiconductor device described in the patent publication, wherein four dummy bumps 105 are provided in each corner of the BGA semiconductor device 103 instead of disposing a single signal bump 104. The dummy bump 105 is bonded onto a reinforcement land formed on the mounting board and onto another reinforcement land formed on the semiconductor package.
It is noted in the present invention that the technique described in the patent publication may rather cause a larger stress on the signal bumps 104 due to the reinforcement itself provided by the reinforcement bumps 105, the larger stress being caused by the ununiform arrangement of the bumps.